The following applications are hereby incorporated herein by reference in their entirety and made part of the present application:
1) U.S. patent application Ser. No. 09/282,949, filed Apr. 1, 1999;
2) U.S. patent application Ser. No. 09/283,876, filed Apr. 1, 1999;
3) U.S. patent application Ser. No. 09/283,175, filed Apr. 1, 1999.
1. Technical Field
The present invention relates generally to digital image data processing; and, more particularly, it relates to digital image printing.
2. Description of Related Art
Conventional digital image printing systems, in that they commonly employ parallel image data processing to image data throughout the digital image printing system, inherently require a significant dedication of real estate within its integrated circuitry. For example, for a digital image printing system that can accommodate a wide variety of image data having varying data sizes. Conventional digital image printing systems that perform bit rotation and row alignment on a group of digital image data perform them sequentially and most commonly using parallel processing circuitry. Typically, bit rotation is performed in one digital image processing step, and row alignment is performed in another digital image data processing step.
Conventional systems will often employ multiple data buffers, one dedicated for each of the two digital image data processing steps, wherein the processing circuitry accesses only one of the data buffers at a time. The conventional process of performing the two functions of bit rotation and row alignment is executed by doing one memory access from the first data buffer, performing digital image data processing using one processing circuit to achieve row alignment, then using a direct memory access channel to transfer the row aligned digital image data to another processing circuit to perform bit rotation. This direct memory access channel, accompanied with the sequential manner of performing the two functions of bit rotation and row alignment, is inherently space consumptive within integrated circuitry of a digital image printing system. Additionally, given the large number of data buffers that are required to perform the data management to perform these two functions independently and sequentially, a large amount of valuable integrated circuitry real estate is consumed. This increases the size of integrated circuitry that performs this digital image data processing of the digital image data.
Conventional digital image printing systems perform extensive preprocessing using a host before transmitting the digital image data to the digital image printing system for printing. The preprocessing includes, among other things, data preparation in a proper format to interface with the processing circuitry having a predetermined number of data channels. This data preparation is required in large part due to the parallel processing circuitry employed within conventional digital image printing systems.
Another disadvantage is when performing image data processing in an intrinsically parallel manner, different logic circuitry is required to deal with each digital image printing system having varying physical and mechanical characteristics such as different number of ink jet nozzles. To accommodate image data processing within each of the different digital image printing systems having different physical and mechanical characteristics, additional logic circuitry is required to provide image data processing for each of the various possible digital image printing systems. This large dedication of parallel processing circuitry, for each of the possible digital image printing systems in which the image processing circuitry may be installed, greatly increases the size, and therefore the cost, of an integrated circuit used to perform these image data processing functions, as described above.
Conventional digital image printing systems commonly perform a number of functions, some of which are highly computationally intensive. The conventional manner of dedicating a fixed amount of parallel logic circuitry to perform each of the functions within the digital image printing system inherently leads to unused portions of logic circuitry on a potentially significant portion of an integrated circuit. In addition, the performance of certain functions within digital image printing system require significantly more logic circuitry, at certain times, for their respective functions than for other functions. This typically results in slowed overall image data processing within the digital image printing system.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
Various aspects of the present invention can be found in a printer that prints digital image data. The printer contains a memory that stores the digital image data for processing in preparation to final printing. The digital image data is partitioned into a first portion of image data and a second portion of image data. Processing circuitry performs row alignment on the first portion of the image data and bit rotation on the second portion of the image data. In certain embodiments of the invention, the processing circuitry is partitioned into a first processing circuit and a second processing circuit. A direct memory access controller is used in other embodiments of the invention to store the first portion of image data into the memory and to retrieve the second portion of image data from the memory.
The printer is an ink jet printer in certain embodiments of the invention. A data register is used to store the image data prior to ink jet firing. The memory that is used to perform the image data processing on the digital image data is made up of two groups of memory buffers in one embodiment. Each memory group has at least one even memory buffer and at least odd even memory buffer. The memory is a crossing group ping pong buffer. The image data that is used in the invention is provided by any number of devices capable of providing digital image data including, among other things, by a computing device.
In certain embodiments of the invention wherein the processing circuitry is partitioned into a first processing circuit and a second processing circuit, the first processing circuit performs row alignment on a portion of the image data, and the second processing circuit performs bit rotation on the same portion of the image data.
In certain embodiments of the invention, the printer is contained within a multi-functional peripheral. The multi-functional peripheral device is a peripheral device containing a plurality of internal devices wherein each of the devices operates either independently or cooperatively to process the plurality of image data. Alternatively, the printer is contained within a stand alone device performing primarily digital image printing. The stand alone device interfaces with additional peripheral devices, including a computing device, if desired.
Other aspects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.